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Job description
We’re looking for a Principal RFIC Design Engineer - Chip Lead to own top-level integration of our next-generation multi-channel beamformer ICs. You’ll drive chip architecture, floorplanning, block integration, top-level RF/analog performance, physical implementation, package interfaces, and tapeout readiness across RF, analog, digital, layout, and test functions.
This is a senior technical leadership role for an experienced IC designer who can see the whole chip. You’ll work directly with the founding engineers and block owners to turn system requirements into a manufacturable, testable product and drive execution from architecture and floorplan through sign-off, silicon bring-up, and customer deployment.
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Worksite address
mountain view, CA, 94039, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.