About this opportunity
SmartRecruiters, Inc. lists this Principal Verification Architect (DDR6 & SystemVerilog/UVM) opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Renesas Electronics is seeking a Principal Design Verification Engineer to provide technical leadership for verification of next-generation semiconductor memory interface products, including data buffers.
The role drives verification strategy and execution for complex digital designs, collaborating with RTL and design teams to ensure functionality, performance and product requirements are met. Deep SystemVerilog and UVM expertise are essential, with DDR memory experience a plus.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.