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Job description
About Hark
Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory.
We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world.
To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems.
About the Role
Build deep understanding of target workloads and characterize their compute, memory, bandwidth, and latency demands on a variety of target hardware platforms
Model performance at every level — silicon, system, service, and end-to-end user experience — and connect insights across layers
Develop and maintain analytical and simulation-based models that project system performance across design and assumption variants
Collaborate with silicon, software, hardware, model, and service teams to align assumptions and deliver insights
Validate models against measured workload behavior and continuously improve fidelity
Translate findings into clear, actionable recommendations for architects, engineers, and leadership
Proactively identify performance risks and design opportunities ahead of architectural commit points
Requirements
5+ years analyzing workload behavior and modeling system performance for consumer or data center products
BS in Computer Science, Electrical Engineering, or related technical discipline
Hands-on experience with profiling, benchmarking, and tracing tools across the stack
Strong programming skills in Python and at least one systems language (C/C++/Rust)
Demonstrated ability to translate quantitative analysis into architectural recommendations
Bonus Qualifications
MS or PhD in a relevant technical discipline
Experience with hardware/software co-design and architectural exploration tooling
Familiarity with accelerator, SoC, or memory subsystem architecture
Comfort moving fluidly between rigorous quantitative work and cross-functional influence
Curiosity, technical depth, and a bias toward learning new system domains quickly
Compensation
The US base salary range for this full-time position is between $120,000 - $300,000 annually.
The pay offered for this position may vary based on several individual factors, including job-related knowledge, skills, and experience. The total compensation package may also include additional components/benefits depending on the specific role. This information will be shared if an employment offer is extended.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.