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Job description
Product Technical Chip Lead, Senior Director
San Jose, California, United States
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at .
Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle.
As the technical integrator for the product line, you will lead through influence and cross-functional authority, working oncutting-edgeUALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world.You'llbe the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon tocustomersenabling rack-scale AI and hyperscale data centers.
Location - San Jose, CA OR Israel
Key Responsibilities
Product Technical Ownership
Own the full technical lifecycle of the product line - architecture assumptions, design integration, validation strategy, readiness, and customer enablement
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, andtapeoutmilestones are met
Lead development of large-scale chips (300-400mm²)utilizing2.5D/3D advanced packaging technologies and chiplet-based architectures
Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths
Own the ChipTapeoutand Chip signoff with full responsibility on Chip Quality.
Cross-Functional Technical Leadership
Anticipate challenges early, drive alignment across all engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved at the earliest
Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria
Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies
Work closely with physical design teams on timing closure, power optimization, and backend execution
Process Excellence & Organizational Development
Establish and reinforce scalable processes, documentation, and handoffs that support company growth
Provide structured, data-driven decision-making andmaintaina crisp operational cadence across the product line
Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration
Model steady, calm leadership, particularly in high-stakes or ambiguous situations
Shape engineering culture and talent strategy to support Astera's rapid growth trajectory
Basic Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
15+ years of experience across architecture, silicon design, validation, systems, or related domains
Proventrack recordof developing large-scale chips (300mm²+) through successfultapeout
Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures
Strong understanding of RTL design, design verification, DFT, and physical design flows
Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures
Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership
Strong communicationand executive presence with the ability to influence at all levels of the organization
Preferred Qualifications
Master's degree in Electrical Engineering or Computer Engineering
Experience withUALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures
Experience with advanced process nodes (7nm, 5nm, or below)
Background in power management, clocking architectures, or high-speed analog integration
Experienceoperatingin fast-growing startups or hyper-scale environments
Systems Thinking: See the big picture while managing details
Emotional Intelligence: Calm under pressure, empathetic, and influential
Adaptability: Thrive in ambiguity and fast-changing environments
Execution Discipline: Deliver predictable results without sacrificing innovation
Base salary range is $260,000 to $295,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.