About this opportunity
Broadcom Inc. lists this R&D Digital Design Engineer opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
About the Role
The CSG group at Broadcom has brought some of the most complex and cutting edge networking ASICs and multi‑chip solutions to market over the last decade. The group develops Tomahawk ASICs for Scale‑Out and Scale‑Up AI Networks. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic of the order of several hundreds of terabits per second. These networking ASICs support a large number of ports ranging from 10/100Mb/s to 1600Gb/s speeds as well as various line interfaces and protocols.
Responsibilities
Participating in the verification processes of L2/L3 network switching and routing ASICs and various subsystems within these chips.
Understanding the architecture and implementation of these chips and coming up with in‑depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems.
Developing verification environments including testbenches and verification APIs associated with the chip architecture to enable testing of various features within the chips as well as scripts and makefiles as required to run the environment in various tool chains.
Implementing test plans into executable test suites using a cutting‑edge SystemVerilog verification environment.
Executing the verification process to completion pre‑silicon using various functional and code‑coverage metrics as measures of completion.
Qualifications
MSEE or BSEE or equivalent, with concentration in digital design and excellent academic standing. Experience requirements: 8+ years for a BS degree, 6+ years for an MS degree, 3+ years for a PhD or equivalent.
Familiar with hardware description languages (Verilog/SystemVerilog/UVM), scripting languages (Perl, Python) and object‑oriented programming (OOP).
Exposure to cutting‑edge verification and validation techniques and methodologies using object‑oriented modular reusable environments in languages such as SystemVerilog, Perl, Python.
Strong understanding and prior experience of end‑to‑end verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production.
Excellent verbal and written communication skills.
Compensation and Benefits
The annual base salary range for this position is $121,900 – $195,000. The employee is eligible for a discretionary annual bonus and the opportunity to receive a competitive new‑hire equity grant as well as annual equity awards. Broadcom offers a comprehensive benefits package, including medical, dental and vision plans, 401(k) participation with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave and vacation time. The company follows all applicable laws for paid family leave and other leaves of absence.
Equal Employment Opportunity
Broadcom is proud to be an equal‑opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
Applicants located outside the USA should provide a home address for future correspondence.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.