About this opportunity
Advanced Micro Devices , Inc. lists this RTL Design Manager opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we'll advance your career.
THE ROLE:
As an RTL Design Manager for the AECG IP & SOC group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.
THE PERSON:
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBLITIES:
Lead a small, high-performance engineering team
Own the design and implementation of blocks to meet functional, timing, area and power requirements
Guide and review verification for these blocks
Design and implement logic functions that enable efficient test and debug
Implement automation to increase design team efficiency
Strong front-end RTL engineering background
Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers
Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiment
PREFERRED EXPERIENCE: Experience with Arm architecture and APB, AXI, CHI protocols
Experience with design reuse, including RTL, constraints, and waivers
Experience with SoC level design integration
Experience with automation using scripting techniques such as PERL, Python, or Tcl
Experience with timing constraints and timing exceptions
Experience running standard quality checks such as LINT and CDC
Experience designing with multiple power domains including writing UPF
Must be a self-starter and self-motivated
ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION:
San Jose, CA
This role is not eligible for visa sponsorship.
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.
Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.