RTL Memory Subsystem Architect for AI Chips

Job description

Architect Labs is seeking a Technical Staff member in Palo Alto to own the memory subsystem RTL end-to-end for production silicon. You’ll architect controllers for DDR5/LPDDR5X and HBM3, drive timing closure, and collaborate with DV, SW, and ML teams.

You’ll refine memory hierarchy, implement near-memory accelerators, and ensure bandwidth, latency, and power targets are met in ML workloads. Strong SystemVerilog and PPA ownership are essential.

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Worksite address

palo alto, CA, 94306, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.