About this opportunity
Renesas Electronics Corporation lists this Senior Advanced Packaging Engineer: 2.5D/3D SiP & WLP opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Renesas Electronics Corporation seeks a Senior Advanced Packaging Engineer to lead next-generation packaging for high-performance semiconductors. You will drive architectures, assembly flows, and reliability, collaborating with design, manufacturing, and suppliers.
You will guide simulations (SI/PI, thermal, mechanical), oversee NPI, qualification, and yield improvements while mentoring junior engineers in a global team.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.