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Job description
Broadcom Irvine seeks an experienced engineer to develop Digital-Mixed Signal (DMS) models for analog IPs using SystemVerilog. You will collaborate with analog design and DV teams to verify chip functionality and ensure robust mixed-signal behavior.
The role requires Verilog-AMS expertise, SV UDT/UDR proficiency, and hands-on scripting with TCL/Perl/Python. Experience with Cadence tools and AI-assisted modeling is a plus.
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Worksite address
irvine, CA, 92713, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.