About this opportunity
Broadcom Inc. lists this Senior Analog/Mixed-Signal Verilog Modeling Engineer opportunity in irvine, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Broadcom Inc. in Irvine seeks an experienced DMS model developer to create Digital‑Mixed Signal models for analog IPs using SystemVerilog. You will interface with analog design and DV teams to support verification, and leverage Verilog‑AMS for modeling and Cadence tools for linting and simulation.
The role requires a strong background in RTL/DTL coding, testbench creation, and hands‑on scripting (TCL/Perl/Python) with exposure to AI-assisted modeling approaches.
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Worksite address
irvine, CA, 92713, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.