About this opportunity
Intel Corporation lists this Senior Applications and Solutions Engineer - Foundry Services opportunity in phoenix, Arizona. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Position Overview
We seek a Senior ASIC Design Engineer who will provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and perform ASIC physical design execution focused on complex multi-voltage domain (UPF/CPF) designs and power-intent (VCLP and Conformal LP) verification signoff. This role drives quality improvements in design kits, supports customers through successful tape-outs, and performs ASIC design services on complex multi-voltage domain designs.
Key Responsibilities
Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologies in multi-voltage domain implementation and verification.
Support and deliver ASIC/Digital tool/flow/methodology solutions, especially in multi-voltage domain design implementation and verification using Cadence and Synopsys tool suites.
Have deep knowledge of UPF/CPF (level-shifter, isolation, power gating, retention, always-on) implementation and verification using VCLP and Conformal LP; write and debug UPF/CPF for multi-voltage domain designs.
Drive customer success through expert guidance and hands-on experience in ASIC design execution.
Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review.
Create application notes, technical design checklists, and deliver training presentations to customers and internal teams.
Establish and maintain high-quality design through implementation and verification methodologies and checklists.
Core Competencies
Self-driven and results-oriented with ability to manage multiple tasks effectively.
Strong teamwork skills to drive solutions for implementation challenges.
Excellent analytical problem-solving capabilities for complex design issues.
Effective communication skills with experience in collaboration and customer feedback.
Minimum Qualifications
US citizenship required.
Ability to obtain a US Government Security Clearance.
Bachelor’s degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
4+ years of experience with advanced CMOS processes (16 nm and below).
3+ years of experience in ASIC design implementation and verification in low power, multi-voltage domain.
3+ years of experience in scripting languages such as Python, Perl, Tcl, and/or shell scripting.
Preferred Qualifications
Active US Government Security Clearance with at least Secret level.
Post-graduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
Experience with state-of-the-art process technology (7 nm and below).
Hands-on experience in physical design implementation and verification methodology for multi-voltage domain in SoC design.
Experience using EDA tools for multi-power domain design (UPF/CPF) implementation and power-intent verification (VCLP, Conformal LP) at block and SOC level.
Experience in writing and debugging UPF/CPF for multi-voltage domain designs.
Customer-facing experience in technical support roles.
Benefits and Work Arrangement
Annual salary range: $122,440.00 – $232,190.00 USD (US locations).
Hybrid work model allowing split between on-site and off-site work.
EEO Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Worksite address
phoenix, AZ, 85003, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.