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Anysilicon

Senior ASIC AI Engineer

santa clara, CA

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About this opportunity

Anysilicon lists this Senior ASIC AI Engineer opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.

Job description

Job Description:

NVIDIA is seeking a motivated Senior ASIC AI Engineer to enhance GPU ASIC design flows through the development of high-performance Agentic AI systems. This role is pivotal in leveraging cutting-edge AI technologies to impact GPU hardware design significantly. Join a global team dedicated to pushing the boundaries of computing.

Responsibilities:

Develop AI-powered methodologies and agents for generating micro-architecture, RTL, and physical design from specifications.

Utilize AI agents to analyze large datasets and existing codebases to create widely applicable skills.

Evaluate and implement multi-agent collaboration frameworks for generating accurate designs for GPU memory systems.

Collaborate with architects, hardware engineers, and physical design engineers to achieve project goals.

Identify opportunities to integrate AI workflows into existing design processes.

Qualifications:

BS in Electrical Engineering, Computer Engineering, or related fields with 5+ years of experience, or MS with 3+ years of relevant experience.

Direct experience with AI-driven development, including coding agents and Agentic workflows.

Proficiency in AI orchestration tools like LangChain or LlamaIndex and reasoning methodologies.

Experience with System Verilog, RTL, and hardware description languages.

Understanding of ASIC flow, including RTL, verification, logic synthesis, and timing analysis.

Skills:

Familiarity with computer architecture concepts, including caches, arbitration, scheduling policies, and interconnects.

Strong interpersonal and communication skills for effective collaboration across teams.

Tell us what you're building and we'll recommend qualified vendors for your project.

ASIC Design Services

Verification

Packaging & Wafer

Semiconductor IP

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Tell us what you're building and we'll recommend qualified vendors for your project.

ASIC Design Services

Verification

Packaging & Wafer

Semiconductor IP

Work Email

Free No obligation Response within 24 hours

#J-18808-Ljbffr

Worksite address

santa clara, CA, 95053, US

Who can apply

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