About this opportunity
Ayar Labs lists this Senior ASIC Design Engineer – Co-Packaged Optics opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
A cutting-edge technology company in San Jose is seeking an ASIC Sr. Staff Engineer responsible for the design and debug of complex digital subsystems. The ideal candidate will have a BS or MS in Electrical Engineering and over 5 years of experience in ASIC design and verification. Proficiency in Verilog, SystemVerilog, and Python is essential. This role offers an opportunity to work in a fast-paced startup environment with competitive remuneration ranging from $180,000 to $223,000.
#J-18808-Ljbffr
Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.