About this opportunity
Celero Communications, Inc. lists this Senior ASIC Design Engineer: DSP, SerDes & Mixed-Signal opportunity in irvine, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Celero Communications, Inc. in Irvine, CA is seeking a highly skilled ASIC Design Engineer to drive development of high-speed digital ASICs for optical communication systems.
The role focuses on Verilog/SystemVerilog, DSP and SerDes, RTL, and collaborating across Analog, Verification, and Physical Design to deliver tapeout-ready silicon. You will engage in synthesis, timing analysis, CDC, and PPA optimization, with scripting in Python or Tcl to automate flows; 5+ years in digital ASIC design
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Worksite address
irvine, CA, 92713, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.