About this opportunity
Cisco Systems, Inc. lists this Senior ASIC Design Engineer - RTL & Timing Expert opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cisco Systems, Inc. in the United States seeks an experienced ASIC Design professional to drive micro-architecture and Verilog RTL implementations, collaborating across verification and physical design to meet timing, power, and performance goals.
Join the Common Hardware Group to contribute to Silicon One and other platforms powering Cisco’s AI-era hardware. A strong RTL background and relevant degrees are required, with full tapeout experience preferred.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.