About this opportunity
Apple Inc. lists this Senior ASIC Design Engineer — SoC Power & IP opportunity in cupertino, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Apple seeks an ASIC Design Engineer in Cupertino, CA to architect power management for the SoC and to write specifications for IPs. You will design, implement, and debug complex logic and integrate IPs into the SOC, while coordinating with front end teams and software groups.
The role requires a BS with 10+ years in the industry, experience leading a team of logic designers, and strong knowledge of clock domains, system architecture, and power/clock management designs.
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Worksite address
cupertino, CA, 95014, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.