About this opportunity
Trilinear Technologies lists this Senior ASIC Design Engineer - Video IP RTL Architect opportunity in portland, Oregon. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Trilinear Technologies in Portland, OR is seeking an experienced RTL engineer to contribute to the next generation of IP products. You will develop high-quality RTL and SystemVerilog code while collaborating with customers to integrate our designs into their architectures.
The ideal candidate will have 5+ years in RTL development, strong Verilog/SystemVerilog experience, and a proven track record of delivering reliable IP.
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Worksite address
portland, OR, 97204, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.