Senior ASIC DFT Architect - Hybrid Work & SoC IP

Job description

NVIDIA is seeking a Senior ASIC Design Engineer to join the DFT team in Santa Clara. You will own fuse controller and DFT IP design for cutting-edge SoCs, while advancing scalable DFT methods and collaborating across architecture, design, and verification groups.

You will partner with multiple teams to define features, validate through test plans, and support post-silicon bring-up. A strong Verilog background and UVM familiarity are valued assets.

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Worksite address

santa clara, CA, 95053, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.