Senior ASIC DFT Architect – SoC Test & IP Lead

Job description

NVIDIA seeks a Senior ASIC Design Engineer to join the DFT team in the US. You will own fuse controller and DFT IP design for leading SoC projects, collaborating with architects and backend teams to ensure cohesive integration.

Responsibilities include developing scalable DFT methodologies, supporting post-silicon bring-up, and mentoring junior engineers. Requires 8+ years in SoC RTL/verification, Verilog, and scripting with Python/Perl/Tcl; UVM is a plus.

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Who can apply

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