About this opportunity
Qualcomm lists this Senior ASIC DV Engineer — Tapeouts, UVM & Power opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
A leading technology company in California is seeking an experienced ASIC Design Verification Engineer to oversee the verification lifecycle for digital power IPs. The ideal candidate will have at least 3 years of experience in verification roles and a Bachelor's degree or higher in related fields. This position offers a competitive salary range of $153,200.00 - $229,800.00 with additional benefits including a discretionary bonus program.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.