About this opportunity
Google Inc. lists this Senior ASIC Physical Design Engineer, Full-Chip opportunity in mountain view, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Google Inc. is seeking a Mid-level Physical Design Engineer in Mountain View, CA to drive ASIC RTL2GDS implementation with focus on high performance, power, and area. You will work with cross-functional teams to deliver top-tier silicon features and optimizations for Google's products.
The role requires a Bachelor's in Electrical Engineering, 4 years in physical design, and hands-on experience with synthesis/PnR flows. Strong Verilog/SystemVerilog and scripting skills are highly valued.
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Worksite address
mountain view, CA, 94039, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.