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Job description
A leading semiconductor foundry in Austin, TX is seeking a Senior Engineer, Physical Design (ASIC/SoC Place & Route). This role involves the entire APR implementation flow from RTL-to-GDS, working in a hybrid model with 4 days in the office. Candidates should have a Master’s in Electrical/Computer Science Engineering and 7+ years of industry experience, particularly with TSMC technologies. The offered compensation ranges from $106,500 to $162,000 annually, along with comprehensive benefits.
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Worksite address
austin, TX, 78716, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.