About this opportunity
Anysilicon lists this Senior ASIC Physical Design Lead - RTL-to-GDSII Expert opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cisco's Common Hardware Group in San Jose, CA is seeking a Senior ASIC Physical Design Technical Lead to drive fullchip floorplanning and RTL-to-GDSII implementation for networking ASICs.
The role requires extensive physical design experience, collaboration with RTL, DFT, EDA vendors, and applying low-power methodologies to optimize performance, power, and die size in advanced node processes.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.