About this opportunity
Triple Crown lists this Senior ASIC RTL Designer opportunity in santa clara county, ca, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Job Type: Contract Duration: 6+ Months
Triple Crown is seeking a Senior ASIC RTL Design Engineer to own the microarchitecture and RTL design of complex, high-speed processor blocks. This role involves building IP from the ground up and taking blocks from initial specification through integration and working silicon.
Own ground-up IP and block design from specification through RTL implementation, integration, and silicon bring-up.
Design data paths, control logic, custom logic, and protocol interfaces with a focus on performance, power, and area (PPA).
Define block interfaces, document design decisions, and evaluate microarchitectural trade-offs.
Partner with architecture, verification, physical design, and firmware teams to meet functional, timing, power, and area targets.
Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
~10+ years of ASIC design experience, including substantial block-level RTL design and silicon development.
~ Strong high-speed design experience, ideally with core processor design.
~ Deep understanding of data-path and control logic design and PPA optimization.
Experience using machine learning tools in chip design workflows.
Paid weekly!
~ Health, Dental and Vision Insurance
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Who can apply
Review the original listing for work authorization, qualifications and employer requirements.