About this opportunity
Anysilicon lists this Senior ASIC/VLSI Synthesis Engineer: FrontEnd Timing Expert opportunity in northern, Kentucky. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Marvell is seeking a Senior Staff Engineer to lead ASIC/VLSI synthesis and design in Irvine, CA. You will develop timing constraints, collaborate across RTL, Architecture, DFT, and Analog teams, and own Front-End tasks including Synthesis, UPF, and ECOs to meet power, performance and area targets.
You will drive Physical Aware Synthesis with Fusion Compiler, automate flows with Tcl/Python, and ensureNetlist handoff readiness for PD. Strong scripting and EDA tool experience are required.
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Who can apply
Review the original listing for work authorization, qualifications and employer requirements.