About this opportunity
Applied Materials, Inc. lists this Senior Chip Design Engineer - Tapeouts & IC Validation opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Applied Materials in Santa Clara, CA is seeking an experienced IC Design/Validation professional for a full-time role with up to 20% travel. The position requires deep expertise in chip design and silicon validation, along with experience in multiple tape-outs and strong cross-functional collaboration to address complex engineering challenges.
The role emphasizes proactive problem solving, technical communication, and adherence to project schedules and milestones within a global team.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.