About this opportunity
Qualcomm lists this Senior CPU DFT Engineer - ASIC Test & Debug (DFT/ATPG) opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
A leading tech company is seeking a DFT Engineer to work closely with chip architects and designers on mixed signal and digital VLSI designs. The role involves creating test vectors, validating DFT requirements, and ensuring high test coverage. Ideal candidates will have extensive experience in digital ASIC design, proficiency in Verilog or VHDL, and expertise with Mentor Tessent tools. This position offers a competitive salary range of $142,200 to $213,400, along with a comprehensive benefits package.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.