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Job description
VLSI Design Engineer
Experience: 7+ years BE - ECE / MTech VLSI design Exposure to TSMC 2NP/3NP is must Perform end-to-end physical design flow: Floorplanning Power planning (PG grid, IR) Placement & optimization CTS (Clock Tree Synthesis) Routing Post-route optimization Achieve timing closure across all modes and corners Resolve DRC, LVS, ERC and signoff violations Handle low-power design techniques: Multi-Vt, Multi-voltage (UPF) Power gating, clock gating Perform physical verification and signoff: STA (Primetime) SI / Crosstalk IR drop & EM analysis Work on advanced nodes (7nm, 5nm, 3nm or below) Collaborate with: RTL & Micro-architecture teams DFT & Test engineers Foundry and CAD teams Debug complex timing, congestion, power, and variability issues Drive methodology improvements and automation (scripts/flows)
Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.