Senior DFT ASIC Engineer: Testability & Bring-Up

Job description

Meta in Sunnyvale, CA is hiring an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team.

You will architect DFT strategies from RTL through silicon bring-up, implementing scan insertion, ATPG, MBIST, LBIST, and boundary scan for large-scale infrastructure ASICs, and collaborate with design, physical implementation, and validation teams to meet aggressive quality and time-to-market targets.

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Worksite address

sunnyvale, CA, 94087, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.