Senior DFT Consultant (Tessent)

Job description

Senior DFT Consultant (Tessent)

The Design for Test Consultant will be responsible for supporting the use of Tessent DFT software in the design of complex Application Specific Integrated Circuit (ASIC) designs. As a Design for Test Consultant, you will be part of a team contributing to implementing and verifying DFT features within our Enterprise Customer's (ASIC) products, as well as enabling them to utilize our advanced methodologies around our Tessent tool suite.

Areas of responsibility include delivering consulting services covering a broad range of DFT activities, working with customers to implement and deploy DFT flows centered around Tessent tool, enabling customer adoption of the full capability of Tessent software and methodologies, effectively communicating how Siemens Digital Industries Software products and service offerings address customers' technical objectives, articulating customer's technical requirements and influencing product engineering to shape product direction, building and maintaining ongoing positive relationships with customers, working collaboratively with team members to ensure mutual success, delivering Tessent-based solutions to address our customer's technical and business needs, and occasional travel world-wide to customer sites, primarily within Europe.

Your qualifications & experience include a BSEE or BSCS, or equivalent; MSEE preferred, ASIC Design for Test experience, interest in applying engineering skills in a creative way to solve unique customer challenges, existing Design for Test experience including MBIST, IJTAG, Boundary Scan, Scan, ATPG, Embedded Compression, strong understanding of the overall ASIC design, experience in design flow automation in the Tessent Shell environment, experienced in Memory BIST with repair using Tessent MBIST, experienced with Logic BIST using Tessent Hybrid TK/LBIST, experience with IJTAG (IEEE 1687), ICL/PDL, experience performing boundary scan insertion using Tessent Boundary Scan, experience in ATPG and compression using TestKompress, experience in scan insertion using Tessent Scan, experience in the verification leveraging Tessent generated testbenches using Questa and industry standard simulation tools, experience with tcl scripting, DFT architecture and methodology development is highly desired, RTL design experience is a plus, strong communication skills are essential, and self-motivated and self-disciplined.

Worksite address

austin, TX, 78716, US

Who can apply

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