About this opportunity
Digicomm Semiconductor INC lists this Senior DFT Engineers opportunity in northern, Kentucky. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Run formal verification between synthesized netlist and post DFT netlist.
Generate DFT constraints for backend and Primetime.
Provide BE team with post DFT netlist and associated constraints.
Validation plan and test development.
Generate ATPG Test Patterns.
Block level and soc level patten generation.
Monitor test coverage and pattern counts.
Run ATPG and pattern verification on DFT inserted netlist
MBIST pattern RTL and gate level validation.
Run full MBIST, scan pattern generation and verification (both pre and post layout netlist)
After chip top netlist is available, all block MBIST, scan pattern generation and verification should be run from top level.
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Who can apply
Review the original listing for work authorization, qualifications and employer requirements.