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Job description
Astera Labs in San Jose, CA, seeks Senior Digital Design Engineers to advance front-end circuit design for high-performance network controllers. You will drive RTL, synthesis, IP integration, and block-level verification across PCIe, Ethernet, UALink, and related protocols.
The role requires a strong EE background with a Bachelor's, 3+ years of SoC experience, and hands-on design using Synopsys/Cadence flows. US work authorization is required.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.