Senior Digital Design Engineer

Job description

Silanna Semiconductors is actively seeking an experienced Senior Digital Design Engineer to contribute to the design and development of integrated circuit solutions related to Silanna’s innovative mixed-signal technology.

This position requires participation in all aspects of the IC development cycle including RTL architecture and design, SystemVerilog/UVM verification, design integration, synthesis support, timing analysis, FPGA prototyping, and test bench debug and characterization.

Experience with physical implementation flows including synthesis and place-and-route is highly desirable.

Essential Duties and Responsibilities

The team drives architecture, design, implementation, and verifcation of mixed-signal systems that include circuit blocks such as PLLs, DLLs, VCOs, ADCs, DACs, Filters, clock distribution and/or recovery systems.

Develop RTL designs in Verilog/SystemVerilog for complex digital and mixed-signal integrated circuits

Define and implement verification environments using SystemVerilog and UVM methodologies

Create test plans, constrained-random testbenches, assertions, coverage models, and regression suites

Collaborate with system engineers to optimize circuit designs and system specification trade-offs

Perform block-level and top-level integration and verification

Analyze and debug functional, timing, CDC, reset, and integration issues

Support synthesis, static timing analysis, lint, CDC, and low-power verification flows

Assist with top-level assembly and design tapeout to semiconductor foundry

Collaborate with backend engineers on synthesis, floorplanning, timing closure, and place-and-route activities

Create SystemVerilog models of the analog blocks

Characterize and debug relevant blocks in silicon

Perform bench testing and verification from prototype debug through production release

Report the results of IC design, analysis, and evaluation

Required Skills and Experience

Strong background in RTL design, digital IC architecture, DSP, and functional verification methodologies

Solid understanding of Verilog/SystemVerilog, UVM, digital design fundamentals, clock-domain crossing, reset synchronization, timing closure, and ASIC/SoC

development flows

Familiarity with mixed-signal integration and modeling techniques

Experience with industry-standard EDA tools for simulation, verification, synthesis, PNR, and debug

Experience with bench testing, characterization, and debug of analog/mixed-signal circuits using test/measurement equipment and computer software

Strong technical communication skills including verbal and writing skills

Ability to work effectively in a collaborative, cross-functional engineering environment

Experience

Bachelor’s degree in electrical engineering (BSEE) required with relevant industry experience; Master’s (MSEE) preferred

Preferably 5+ years in digital IC/ASIC design and verification

Required familiarity with working in agent-based (Agentic) AI environments

Exposure to synthesis flows and physical design (e.g., place-and-route, timing closure, power optimization) is a plus

Proficiency in UNIX/Linux and strong Python scripting skills are desirable

Experience with FPGA prototyping and emulation platforms is a plus

Background in mixed-signal design is advantageous

Pay Range and Other Compensation and Benefits

USD $200,000 - $250,000 Annually

This role offers a competitive base salary - reflecting the full range for this location alongside a comprehensive total rewards package. In addition to base pay, compensation includes eligibility for discretionary annual bonuses, plus extensive benefits designed to support your work-life balance.

EEO Employer: Silanna Semiconductor is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Silanna Semiconductor expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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Worksite address

san diego, CA, 92189, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.