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Job description
Digital Mixed-Signal Lead with a strong digital design and architecture background to lead the development of digital control infrastructures for advanced clocking sub-systems (PLLs, FLLs, and DLLs ).
Core Responsibilities
Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs.
Logic Design: Design complex digital control loops, state machines for adaptive calibration, DVFS (dynamic voltage/frequency scaling) controllers, and fractional-N delta-sigma modulators.
Analog Interface: Serve as the primary bridge to Analog Circuit Designers. Translate analog specifications into robust digital architectures and define clean boundaries at the analog-digital interface.
Verification Partnership: Partner with Verification Teams to drive Mixed-Signal Verification (MSV) and Real Number Modeling (RNM) strategies for high-coverage loop simulations.
Physical Design Collaboration: Work with Physical Design Teams to co-optimize floorplanning and protect sensitive analog nodes from digital switching noise.
Sign-off Methodology: Enforce a rigorous full-chip CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) sign-off methodology for the clocking network.
Candidate Requirements
Experience: 8+ years of professional digital ASIC design experience.
RTL Mastery: Deep expertise in writing robust, synthesizable SystemVerilog RTL
Process Nodes: Direct experience with advanced technology nodes, specifically N5, N3P, and beyond .
Track Record: Proven history of steering cross-functional execution from initial concept through to successful tapeouts.
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Worksite address
san francisco, CA, 94199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.