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Job description
Neuralink is seeking a Digital IC Design Engineer to deliver RTL and micro-architecture for low-power digital IPs and systems, focusing on DSPs and hardware accelerators used in brain-computer interfaces. The role demands strong background in micro-architecture, RTL, and energy-aware design across complex digital systems.
You will work with firmware teams to optimize hw/sw interfaces, perform energy/performance analyses, and contribute to silicon bring-up and verification efforts.
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Worksite address
california, MO, 65018, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.