Senior DRAM IO & Clock Design Architect

Job description

Micron Technology, a world leader in memory and storage, seeks a Principal/ MTS IO/Clock Design Engineer to lead high-speed IO and clocking circuit design for DRAM IP. You will drive modeling, verification and optimization, addressing jitter, timing and performance at full-chip level.

Relocation to Micron’s Boise headquarters is required. The role collaborates with design, SI, and process teams, mentoring engineers and advancing next-generation process nodes.

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Worksite address

boise, ID, 83708, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.