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Job description
Cadence is seeking a Senior Engineer for its System Verification Group in California to advance Xcelium RTL/logic simulator. You will design and optimize the simulator to handle AI and hyperscale chip designs, lead junior engineers, and collaborate with a distributed team.
You will work on C/C++ implementations, timing verification, and SDC constraints, writing specifications and unit tests while pushing performance improvements and scalable algorithms for multi-billion-node graphs.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.