About this opportunity
Cadence Design Systems, Inc. lists this Senior EDA Tools Engineer — Timing, ML & Performance opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cadence Design Systems, Inc. is seeking a seasoned software engineer to advance our transistor‑level timing, power, and reliability analysis tools.
You will design new architectures and extend frameworks to handle complex timing challenges in modern chips. With 8+ years in EDA tool development and expert C++ skills in Linux, you will optimize data structures and algorithms while applying best practices for high‑quality software engineering.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.