About this opportunity
Teradyne lists this Senior FPGA Architect - Memory Test Solutions opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our cutting-edge memory test solutions. You will design and implement FPGA-based architectures for next-gen Flash and DRAM instrumentation, combining digital and analog design, and collaborate with cross-functional teams.
You will mentor junior engineers, translate customer needs into robust, scalable FPGA designs, and help maintain existing FPGA portfolios to meet quality
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.