About this opportunity
Teradyne lists this Senior FPGA Design Engineer - Memory Test & RTL Architect opportunity in tualatin, Oregon. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Teradyne’s Memory Test Division seeks an FPGA Engineer to develop next‑generation memory test solutions. You will architect FPGA designs for Flash and DRAM test instrumentation, guide junior engineers, and convert complex customer requirements into robust, extensible implementations.
Ideal candidates have 8+ years in FPGA design, strong RTL/Verilog skills, and experience with FPGA tool flows and lab validation. Occasional travel may be required.
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Worksite address
tualatin, OR, 97062, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.