About this opportunity
Teradyne lists this Senior FPGA Design Engineer (MTD, San Jose, CA) opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Opportunity Overview
Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting‑edge memory test solutions. MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world’s most advanced memory technologies, combining state‑of‑the‑art digital and analog designs, cutting‑edge ASIC/FPGA technologies, liquid cooling, and high‑performance signal delivery.
Responsibilities
Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
Provide technical guidance to junior engineers.
Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
Maintain schedule commitments and deliver high quality end products.
Occasional travel may be required.
All About You
B.S. or M.S. in Electrical Engineering or closely related discipline and 8+ years of relevant work experience.
Experience with Digital Design and Architecture.
RTL coding, synthesis, timing closure and lab validation.
Experience with Static Timing Analysis of ASICs or FPGAs.
Experience with digital simulation testbench creation.
Experience with C or C++.
Additional Desired Skills
Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators.
FPGA Transceiver based design experience.
Experience with DRAM and Flash Memory interfaces.
Experience with Intel/Xilinx FPGA tool flows.
Proficiency with Verilog HDL Language.
Familiarity with UVM Methodology.
Scripting languages experience.
Linux and Windows operating systems experience.
Familiarity with ATE instrumentation.
Compensation
The base salary range for this role is $170,400 – $272,600. This range is a good faith estimate and will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonuses based on financial performance.
Benefits
Teradyne offers a variety of robust health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here ( to see details.
Current openings may involve access to export controlled technology and may be subject to export licensing requirements prior to employment. ATTENTION APPLICANTS WITH DISABILITIES: If you’re unable to access our online application due to a disability you may visit one of our locations or our Corporate Office at 600 Riverpark Drive, North Reading, MA and request a paper application form. In addition, you may also contact the HR Service Center at 978‑370‑3041 or contact them at for additional assistance. LitePoint, a Teradyne Company is an equal‑opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, age, disability status, protected veteran status, or any other characteristic protected by law. We are a VEVRAA Federal Contractor.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.