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Job description
AMD is seeking a performant hardware/firmware engineer in San Jose to architect and implement cutting-edge ASIC/FPGA acceleration solutions. You will design high‑speed RTL, validate complex interfaces, and collaborate across global teams.
The role involves system-level integration, pre/post-silicon verification, and hands-on work with Vivado and UVM in a fast-paced environment. A strong background in digital design and compute acceleration is required.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.