About this opportunity
Achronix Semiconductor Corporation lists this Senior FPGA Test Development Lead | ATE & Yield Optimizer opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
A leading fabless semiconductor company in Santa Clara, California, is seeking a Senior Manager, Test Development Engineering. The role involves leading test program development for FPGA integrated circuits, managing a team, and implementing strategies to optimize yield and cost in production test processes. Ideal candidates will have extensive experience in semiconductor test engineering, strong analytical skills, and proficiency with Advantest V93000 ATE platforms. The company offers a competitive salary and benefits in a dynamic work environment.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.