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Job description
Nokia in San Jose, CA is seeking a PhD/MS level analog/mixed-signal IC designer to bring high-speed ADC/DAC and PLLs to production in CMOS FinFET tech. You will design, simulate, and verify analog circuits and collaborate with layout engineers.
You will create layouts, evaluate topologies for power, area, bandwidth, and work with cross-functional teams to ensure design methodology and release flows. Required: PhD or MS in EE with 3+ years, proficiency with Cadence Virtuoso, Spectre, Calibre, and
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.