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Job description
A cutting-edge technology startup is seeking an IC Packaging Engineer to lead advanced multi-chip packaging solutions for THz-system RFIC and SoC applications. This mid-senior level role involves technical leadership and collaboration in a hybrid work environment based in the Bay Area. Candidates should have over 10 years of experience in IC packaging design, a strong background in RF integration, and a Master's or Ph.D. in a relevant field. The position offers competitive compensation and an opportunity to work on breakthrough ADAS technology.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.