About this opportunity
Arrow Electronics lists this Senior IC Physical Design Engineer - Synthesis to Signoff opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Arrow Electronics is seeking a Physical Design Engineer II to drive ASIC partition implementation, including synthesis, place-and-route, and timing convergence. You will collaborate with architects, RTL designers, and DFT engineers to resolve issues and ensure clean signoffs.
Strong PD flow expertise and TCL scripting are highly valued. The role requires 7+ years in physical design, proficiency with Innovus/Tempus/Quantus, and experience in SoC design and sub-7nm processes.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.