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Job description
A leading semiconductor company is seeking a Senior Technical Leader to shape Memory PHY technology. You will drive architectural direction and technical decisions for cutting-edge designs in mixed-signal circuits and influence critical project outcomes. Ideal candidates will have over 15 years’ experience in analog and mixed-signal design, especially in high-speed technologies. Join a collaborative team that values deep technical ownership and innovation, while shaping the future of computing architecture.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.