About this opportunity
Nutanix lists this Senior Memory Subsystem Verification Engineer opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Qualcomm Technologies, Inc. is seeking a motivated Design Verification Engineer to join its memory subsystem verification team.
You will develop verification strategies, build UVM-based testbenches, and drive coverage closure for high-performance memory interfaces (LPDDR/DDR/HBM) and related PHY logic. The role emphasizes hands-on verification with Verilog, SystemVerilog, UVM, and SVA, spanning the full verification lifecycle from planning to regression and debug.
#J-18808-Ljbffr
Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.