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Job description
Digital Designer
We are hiring an experienced digital designer to work on the next generation NVM (non-volatile memory) controller for analog compute-in memory technology. The candidate will be responsible for the design, development, and verification of NVM IP and digital controllers for Mythic's product architecture. This role collaborates closely with circuit, digital, compiler, firmware, and software teams to define NVM controller architecture, develop and validate behavioral models, and improve RTL design and verification methodologies.
What you'll do
Participate in design and responsible for verifying complete IP macros specifically applicable for Mythic product architecture utilizing the available NVM technologies from foundries
Contribute to next generation NVM digital controller
Responsible for NVM digital controller design, definition, interface, and communications
Work with NVM circuit designers for RNM, functional, and Verilog models of NVM circuits
Drive verifications of RNM and functional models of NVM circuits
Participate in design reviews and contribute to improving RTL coding practices and methodologies.
Work closely with digital, compiler, firmware, and software team to define NVM controller architecture
What you'll bring
Ph.D. or MS degree in EE or related 3+ years industrial experience in RTL design, microarchitecture, and architecture development.
Hands-on experience in full chip digital simulation setup, debugging, and verification
Familiar and hands-on experience on NVM (NOR / NAND / similar) voltage operation and/or programming algorithms, and timing diagram is a plus
Understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies) is a plus.
Experience with one or more of the following subsystems: scheduling fabrics, high-performance interconnects, DMA engines, memory controllers, or datapath/control logic is a plus.
Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling
Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.
Familiarity with timing constraints, physical design considerations, and EDA flows.
Hands-on experience with simulation, synthesis, linting, and static timing analysis tools.
Excellent communication skills, ability to work well across multi-functional teams
$178,000 - $240,000 a year
At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.
Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law.
Worksite address
palo alto, CA, 94306, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.