About this opportunity
Rambus lists this Senior PCIe IP Design Lead (RTL/SystemVerilog) opportunity in hillsboro, Oregon. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Rambus in the United States is seeking a motivated Principal Design Engineer to join the PCIe IP design team. You will contribute to architecture and micro-architecture and implement designs in SystemVerilog, collaborating with an international team.
The role involves prototyping IPs on cutting-edge FPGAs, supporting existing IP generations, and working in a hybrid environment with three onsite days per week. A strong RTL background and Masters/PhD are preferred.
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Worksite address
hillsboro, OR, 97104, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.